ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 345

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

• PAR: Parity Type
• SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase
SYNC = 0: USART operates in Asynchronous Mode.
SYNC = 1: USART operates in Synchronous Mode.
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
• CHRL: Character Length.
• USCLKS: Clock Selection
32058J–AVR32–04/11
0
1
1
0
0
0
0
1
1
– If USART does not operate in SPI Mode (MODE is … 0xE and 0xF):
– If USART operates in SPI Mode (MODE = 0xE or 0xF):
0
0
1
1
0
0
1
1
USCLKS
CHRL
PAR
1
0
1
0
0
1
1
0
1
0
1
0
1
1.5 stop bits
2 stop bits
Reserved
0
1
0
1
0
1
0
1
x
x
Character Length
5 bits
6 bits
7 bits
8 bits
Parity Type
Even parity
Odd parity
Parity forced to 0 (Space)
Parity forced to 1 (Mark)
No parity
Multidrop mode
Selected Clock
CLK_USART
CLK_USART
Reserved
CLK
/DIV (DIV = xx)
Reserved
2 stop bits
Reserved
AT32UC3A
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