ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 226

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 24-9. Master Read with One Data Byte
Figure 24-10. Master Read with Multiple Data Bytes
24.10.6
24.10.6.1
32058J-AVR32-04/11
TXCOMP
RXRDY
TWD
Internal Address
S
7-bit Slave Addressing
Write START Bit
DADR
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (RHR). The RXRDY bit is reset when reading the RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without IADR, the STOP bit must be set after the next-to-last data received.
See
RXRDY is used as Receive Ready for the PDC receive channel.
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
Figure 24-11
The three internal address bytes are configurable through the Master Mode register (MMR).
TXCOMP
RXRDY
R
Figure
TWD
A
24-10. For Internal Address usage see
and
S
DATA n
Write START &
Figure 24.11
STOP Bit
DADR
Read RHR
A
DATA n
for Master Write operation with internal address.
DATA (n+1)
R
A
A
DATA (n+1)
Read RHR
DATA
DATA (n+m)-1
Figure
”Internal Address” on page
Read RHR
N
24-9. When a multiple data byte read is
DATA (n+m)-1
P
A
Read RHR
after next-to-last data read
DATA (n+m)
Write STOP Bit
AT32UC3A
Figure
226.
N
24-12. See
DATA (n+m)
Read RHR
P
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