ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 246
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 246 of 826
- Download datasheet (20Mb)
24.14 Two-wire Interface (TWI) User Interface
24.14.1
Table 24-4.
Note:
24.14.2
Name:
Access:
Reset Value: 0x00000000
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
32058J-AVR32-04/11
Offset
0x00
0x04
0x08
0x0C
0x10
0x20
0x24
0x28
0x2C
0x30
0x34
0x38 - 0xF8
0xFC
0x38 - 0xFC
SWRST
31
23
15
–
–
–
7
1. Values in the Version Register vary with the version of the IP block implementation.
Register Mapping
TWI Control Register
CR
Write-only
TWI User Interface
Register
Control Register
Master Mode Register
Slave Mode Register
Internal Address Register
Clock Waveform Generator Register
Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Receive Holding Register
Transmit Holding Register
Reserved
Version Register
Reserved
30
22
14
–
–
–
6
–
SVDIS
29
21
13
–
–
–
5
SVEN
28
20
12
–
–
–
4
MSDIS
27
19
11
–
–
–
3
TWI_VER
CWGR
Name
MMR
IADR
SMR
RHR
THR
IMR
IER
IDR
CR
SR
–
–
MSEN
26
18
10
–
–
–
2
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Write-only
Read-only
Write-only
Write-only
Write-only
Access
–
–
STOP
25
17
–
–
9
–
1
AT32UC3A
0x00000000
0x0000F009
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
N / A
N / A
N / A
START
–
–
24
16
–
–
8
–
0
(1)
246
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