ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 734
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 734 of 826
- Download datasheet (20Mb)
35. On-Chip Debug
35.1
35.2
32058J–AVR32–04/11
Features
Overview
Rev: 1.3.0.0
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Debugging on the AT32UC3A is facilitated by a powerful On-Chip Debug (OCD) system. The
user accesses this through an external debug tool which connects to the JTAG port and the Aux-
iliary (AUX) port. The AUX port is primarily used for trace functions, and a JTAG-based
debugger is sufficient for basic debugging.
The debug system is based on the Nexus 2.0 standard, class 2+, which includes:
In addition to the mandatory Nexus debug features, the AT32UC3A implements several useful
OCD features, such as:
The OCD features are controlled by OCD registers, which can be accessed by JTAG when the
NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access OCD registers directly
using mtdr/mfdr instructions in any privileged mode. The OCD registers are implemented based
on the recommendations in the Nexus 2.0 standard, and are detailed in the AVR32UC Technical
Reference Manual.
• Basic run-time control
• Program breakpoints
• Data breakpoints
• Program trace
• Ownership trace
• Data trace
• Debug Communication Channel between CPU and JTAG
• Run-time PC monitoring
• CRC checking
• NanoTrace
• Software Quality Assurance (SQA) support
Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
JTAG access to all on-chip debug functions
Advanced Program, Data, Ownership, and Watchpoint trace supported
NanoTrace JTAG-based trace access
Auxiliary port for high-speed trace information
Hardware support for 6 Program and 2 Data breakpoints
Unlimited number of software breakpoints supported
Automatic CRC check of memory regions
AT32UC3A
734
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