ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 613
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 613 of 826
- Download datasheet (20Mb)
30.8.3.11
Offset:
Register Name:
Access Type:
Reset Value:
• PENX, X in [0..6]: Pipe X Enable
Set to enable the Pipe X.
Clear to disable the Pipe X, what forces the Pipe X state to inactive and resets the pipe X registers (UPCFGX, UPSTAX,
UPCONX) but not the pipe configuration (ALLOC, PBK, PSIZE).
• PRSTX, X in [0..6]: Pipe X Reset
Set by software to reset the Pipe X FIFO.
This resets the endpoint X registers (UPCFGX, UPSTAX, UPCONX) but not the endpoint configuration (ALLOC, PBK,
PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle management
.
The endpoint configuration remains active and the endpoint is still enabled.
Then, clear by software to complete the reset operation and to start using the FIFO.
32058J–AVR32–04/11
31
23
15
–
–
–
7
–
USB Pipe Enable/Reset Register (UPRST)
PRST6
PEN6
rwu
30
22
14
rw
–
0
–
6
0
PRST5
PEN5
rwu
29
21
13
rw
–
0
–
5
0
0x0041C
UPRST
Read/Write
0x00000000
PRST4
PEN4
rwu
28
20
12
rw
–
0
–
4
0
PRST3
PEN3
rwu
27
19
11
rw
–
0
–
3
0
PRST2
PEN2
rwu
26
18
10
rw
–
0
–
2
0
PRST1
PEN1
rwu
25
17
rw
–
0
9
–
1
0
AT32UC3A
PRST0
PEN0
rwu
24
16
rw
–
0
8
–
0
0
613
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