ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 331
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 331 of 826
- Download datasheet (20Mb)
26.7.6.3
Figure 26-35. IrDA Demodulator Operations
32058J–AVR32–04/11
CLK_USART
Receiver
Counter
Value
Input
RXD
IrDA Demodulator
6
5
4
Rejected
Table 26-10. IrDA Baud Rate Error (Continued)
The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is
loaded with the value programmed in IFR. When a falling edge is detected on the RXD pin, the
Filter Counter starts counting down at the CLK_USART speed. If a rising edge is detected on the
RXD pin, the counter stops and is reloaded with IFR. If no rising edge is detected when the
counter reaches 0, the input of the receiver is driven low during one bit time.
Figure 26-35 on page 331
As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in FIDI
must be set to a value higher than 0 in order to assure IrDA communications operate correctly.
Pulse
Peripheral Clock
3 686 400
20 000 000
32 768 000
40 000 000
3 686 400
20 000 000
32 768 000
3
2
6
6
5
Baud Rate
4
9 600
9 600
9 600
9 600
2 400
2 400
2 400
illustrates the operations of the IrDA demodulator.
3
2
1
0
Accepted
Pulse
130
213
260
521
853
CD
24
96
Driven Low During 16 Baud Rate Clock Cycles
Baud Rate Error
0.00%
0.16%
0.16%
0.16%
0.00%
0.03%
0.04%
AT32UC3A
Pulse Time
19.53
19.53
19.53
19.53
78.13
78.13
78.13
331
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