AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 133
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
AT32UC3L-EK
Manufacturer Part Number
AT32UC3L-EK
Description
KIT EVAL AVR32 UC3 MCU
Manufacturer
Atmel
Type
MCUr
Specifications of AT32UC3L-EK
Contents
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
UC3L
Kit Contents
Board
Features
USB / Battery Powered, Board Controller / Bootloader
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Tool Type
Starter Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor Series
AT32
Processor To Be Evaluated
AT32UC3L064
Interface Type
USB, Capacitive Touch
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L-EK
Manufacturer:
Atmel
Quantity:
135
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10.5.2
Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
32099F–11/2010
ARBT: Arbitration Type
FIXED_DEFMSTR: Fixed Default Master
DEFMSTR_TYPE: Default Master Type
SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
31
23
15
–
–
–
7
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master
which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
0: No Default Master
At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in a one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having
accessed it.
This results in not having one cycle latency when the last master tries to access the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number
that has been written in the FIXED_DEFMSTR field.
This results in not having one cycle latency when the fixed master tries to access the slave again.
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking a very slow slave when very long bursts are used.
This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing
any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
Slave Configuration Registers
30
22
14
SCFG0...SCFG15
Read/Write
0x40 - 0x7C
0x00000010
–
–
–
6
29
21
13
–
–
5
28
20
12
–
–
4
FIXED_DEFMSTR
SLOT_CYCLE
27
19
11
–
–
3
26
18
10
–
–
2
AT32UC3L016/32/64
25
17
–
9
–
1
DEFMSTR_TYPE
ARBT
24
16
8
–
0
133
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