AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 492

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.9.8
Name:
Access Type:
Offset:
Reset Value:
• MENB: Master Interface Enable
• STOP: Stop Request Accepted
• PECERR: PEC Error
• TOUT: Timeout
• SMBALERT: SMBus Alert
• ARBLST: Arbitration Lost
• DNAK: NAK in Data Phase Received
• ANAK: NAK in Address Phase Received
• BUSFREE: Two-wire Bus is Free
32099F–11/2010
31
23
15
7
-
-
-
-
0: Master interface is disabled.
1: Master interface is enabled.
This bit is set when STOP request caused by setting CR STOP has been accepted, and transfer has stopped.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when a SMBus PEC error occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when a SMBus timeout occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when an SMBus Alert was received.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when the actual state of the SDA line did not correspond to the data driven onto it, indicating a higher-priority
transmission in progress by a different master.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when no ACK was received form slave during data transmission.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when no ACK was received from slave during address phase
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is set when activity has completed on the two-wire bus.
Otherwise, this bit is cleared.
Status Register (SR)
STOP
30
22
14
6
-
-
-
SR
Read-only
0x1C
0x00000002
BUSFREE
PECERR
29
21
13
5
-
-
TOUT
IDLE
28
20
12
4
-
-
SMBALERT
CCOMP
27
19
11
3
-
-
ARBLST
CRDY
26
18
10
2
-
-
AT32UC3L016/32/64
TXRDY
DNAK
25
17
9
1
-
-
RXRDY
MENB
ANAK
24
16
8
0
-
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