AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 251

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.2
14.5.4
32099F–11/2010
Peripheral events
Alarm interrupt
prescaler when the AST is enabled. The bit is selected by the Interval Select field in the corre-
sponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of
where f
The corresponding PERn bit in the Status Register (SR) will be set when the selected bit in the
the prescaler has a 0-to-1 transition.
Because of synchronization, the transfer of the INSEL value will not happen immediately. When
changing/setting the INSEL value, the user must make sure that the prescaler bit number INSEL
will not have a 0-to-1 transition before the INSEL value is transferred to the register. In that case,
the first periodic interrupt after the change will not be triggered.
The AST can also generate alarm interrupts. If the ALARMn bit in IMR is one, the AST will gen-
erate an interrupt request when the counter value matches the selected alarm value, when the
AST is enabled. The alarm value is selected by writing the value to the VALUE field in the corre-
sponding Alarm Register (ARn.VALUE).
The corresponding ALARMn bit in SR will be set when the counter reaches the selected alarm
value.
Because of synchronization, the transfer of the alarm value will not happen immediately. When
changing/setting the alarm value, the user must make sure that the counter will not count the
selected alarm value before the value is transferred to the register. In that case, the first alarm
interrupt after the change will not be triggered.
If the Clear on Alarm bit in the Control Register (CR.CAn) is one, the corresponding alarm inter-
rupt will clear the counter and set the OVF bit in the Status Register. This will generate an
overflow interrupt if the OVF bit in IMR is set.
The AST can generate a number of peripheral events:
The PERn peripheral event(s) is generated the same way as the PER interrupt, as described in
Section
interrupt, as described in
way as the OVF interrupt, as described in
• OVF
• PER0
• PER1
• ALARM0
• ALARM1
CS
14.5.3.1. The ALARMn peripheral event(s) is generated the same way as the ALARM
is the frequency of the selected clock source.
Section
14.5.3.2. The OVF peripheral event is generated the same
f
PA
Section
=
------------------------ -
2
INSEL
f
CS
14.5.3-
+
1
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