AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 840
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AT32UC3L-EK
Manufacturer Part Number
AT32UC3L-EK
Description
KIT EVAL AVR32 UC3 MCU
Manufacturer
Atmel
Type
MCUr
Specifications of AT32UC3L-EK
Contents
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
UC3L
Kit Contents
Board
Features
USB / Battery Powered, Board Controller / Bootloader
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Tool Type
Starter Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor Series
AT32
Processor To Be Evaluated
AT32UC3L064
Interface Type
USB, Capacitive Touch
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L-EK
Manufacturer:
Atmel
Quantity:
135
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- Download datasheet (13Mb)
35.4.15
35.4.16
32099F–11/2010
PWMA
TC
1. PARAMETER register reads 0x2424
2. Open drain mode does not work
3. VERSION register reads 0x100
4. Writing to the duty cycle registers when the timebase counter overflows can give an
5. BUSY bit is never cleared after writes to the Control Register (CR)
6. Incoming peripheral events are discarded during duty cycle register update
1. When the main clock is RCSYS, TIMER_CLOCK5 is equal to CLK_PBA
Use an external inverter to invert the signal going into the TWIM. When using both TWIM
and TWIS on the same pins, the SMBAL cannot be used.
The PARAMETER register reads 0x2424 instead of 0x24.
Fix/Workaround
None.
The open drain mode does not work.
Fix/Workaround
None.
The VERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
undefined result
The duty cycle registers will be corrupted if written when the timebase counter overflows. If
the duty cycle registers are written exactly when the timebase counter overflows at TOP, the
duty cycle registers may become corrupted.
Fix/Workaround
Write to the duty cycle registers only directly after the Timebase Overflow bit in the status
register is set.
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is
disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never
cleared.
Fix/Workaround
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the
PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN.
Incoming peripheral events to all applied channels will be discarded if a duty cycle update is
received from the user interface in the same PWMA clock period.
Fix/Workaround
Ensure that duty cycle writes from the user interface are not performed in a PWMA clock
period when an incoming peripheral event is expected.
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to CLK_PBA and
not CLK_PBA/128.
Fix/Workaround
None.
AT32UC3L016/32/64
840
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