AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 281

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.5.3
15.5.4
15.5.5
32099F–11/2010
Disabling the WDT
Flash Calibration
Special Considerations
The WDT is disabled by writing a zero to the CTRL.EN bit. When disabling the WDT no other
bits in the CTRL Register should be changed until the CTRL.EN bit reads back as zero. If the
CTRL.CEN bit is written to zero, the CTRL.EN bit will never read back as zero if changing the
value from one to zero.
The WDT can be enabled at reset. This is controlled by the WDTAUTO fuse. The WDT will be
set in basic mode, RCSYS is set as source for CLK_CNT, and PSEL will be set to a value giving
T
how to program the fuses.
If the Flash Calibration Done (FCD) bit in the CTRL Register is zero at a watchdog reset the
flash calibration will be redone, and the CTRL.FCD bit will be set when the calibration is done. If
CTRL.FCD is one at a watchdog reset, the configuration of the WDT will not be changed during
flash calibration. After any other reset the flash calibration will always be done, and the
CTRL.FCD bit will be set when the calibration is done.
Care must be taken when selecting the PSEL/TBAN values so that the timeout period is greater
than the startup time of the chip. Otherwise a watchdog reset will reset the chip before any code
has been run. This can also be avoided by writing the CTRL.DAR bit to one when configuring
the WDT.
If the Store Final Value (SFV) bit in the CTRL Register is one, the CTRL Register is locked for
further write accesses. All writes to the CTRL Register will be ignored. Once the CTRL Register
is locked, it can only be unlocked by a reset (e.g. POR, OCD, and WDT).
The CTRL.MODE bit can only be changed when the WDT is disabled (CTRL.EN=0).
psel
above 100 ms. Please refer to the Fuse Settings chapter for details about WDTAUTO and
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