AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 613

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.8
26.8.1
26.8.2
26.8.3
32099F–11/2010
Operating Modes
Conversion Triggers
ADC Mode
Resistive Touch Screen Mode
The ADCIFB features two operating modes, each defining a separate conversion sequence:
The operating mode is selected by the TSAMOD field in the Mode Register (MR).
A conversion sequence is started either by a software or by a hardware trigger. When a conver-
sion sequence is started, all enabled channels will be converted and made available in the
shared Last Converted Register (LCDR).
The software trigger is asserted by writing a one to the START field in the Control Register (CR).
The hardware trigger can be selected by the TRGMOD field in the Trigger Register (TRGR). Dif-
ferent hardware triggers exist:
Enabling a hardware trigger does not disable the software trigger functionality. Thus, if a hard-
ware trigger is selected, the start of a conversion can still be initiated by the software trigger.
In the ADC Mode, the active channels are defined by the Channel Status Register (CHSR). A
channel is enabled by writing a one to the corresponding bit in the Channel Enable Register
(CHER), and disabled by writing a one to the corresponding bit in the Channel Disable Register
(CHDR). The conversion results are stored in the Last Converted Data Register (LCDR) as they
become available, overwriting old conversions.
At each trigger, the following sequence is performed:
If the Peripheral DMA Controller is enabled, all converted values are transferred continuously
into the memory buffer.
Writing a one to the TSAMOD field in the Mode Register (MR) enables Resistive Touch Screen
Mode. In this mode the channels TSPO+0 to TSPO+3, corresponding to the resistive touch
• ADC Mode: At each trigger, all the enabled channels are converted.
• Resistive Touch Screen Mode: At each trigger, all enabled channels plus the resistive touch
• External trigger, either rising or falling or any, detected on the external trigger pin TRIGGER
• Pen detect trigger, depending the PENDET bit in the Mode Register (MR)
• Continuous trigger, meaning the ADCIFB restarts the next sequence as soon as it finishes
• Periodic trigger, which is defined by the TRGR.TRGPER field
• Peripheral event trigger, allowing the Peripheral Event System to synchronize conversion with
1. If ACR.SLEEP is one, wake up the ADC and wait for the startup time.
2. If Channel 0 is enabled, convert Channel 0 and store result in LCDR.
3. If Channel 1 is enabled, convert Channel 1 and store result in LCDR.
4. If Channel N is enabled, convert Channel N and store result in LCDR.
5. If ACR.SLEEP is one, place the ADC cell in a low-power state.
screen channels are converted as described in
dedicated resistive touch screen channels are enabled, they are converted normally before
and after the resistive touch screen channels are converted.
the current one
some configured peripheral event source.
Section
AT32UC3L016/32/64
26.8.3. If channels except the
613