AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 834

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

35.4.7
32099F–11/2010
SCIF
11. Requesting clocks in idle sleep modes will mask all other PB clocks than the
1. The DFLL should be slowed down before disabled
2. Writing to ICR masks new interrupts received in the same clock cycle
3. FINE value for DFLL is not correct when dithering is disabled
4. BODVERSION register reads 0x100
5. BRIFA is non-functional
6. VREGCR.DEEPMODEDISABLE bit is not readable
7. DFLL step size should be 7 or lower below 30 MHz
-The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and
OSCCTRL0.MODE == 0)
-A sleep mode where the OSC0 is automatically disabled is entered
-The chip enters sleep walking
Fix/Workaround
Do not run OSC0 in external clock mode if sleep walking is expected to be used.
requested
In idle or frozen sleep mode, all the PB clocks will be frozen if the TWIS or the AST need to
wake the CPU up.
Fix/Workaround
Disable the TWIS or the AST before entering idle or frozen sleep mode.
The frequency of the DFLL should be set to minimum before disabled.
Fix/Workaround
Before disabling the DFLL the value of the COARSE register should be set to zero.
Writing to ICR masks any new SCIF interrupt received in the same clock cycle, regardless of
write value.
Fix/Workaround
For every interrupt except BODDET, SM33DET, and VREGOK the CLKSR register can be
read to detect new interrupts. BODDET, SM33DET, and VREGOK interrupts will not be gen-
erated if they occur when writing to ICR.
In open loop mode, the FINE value used by the DFLL DAC is offset by two compared to the
value written to the DFLL0CONF.FINE field. I.e. the value to the DFLL DAC is
DFLL0CONF.FINE-0x002. If DFLL0CONF.FINE is written to 0x000, 0x001, or 0x002 the
value to the DFLL DAC will be 0x1FE, 0x1FF, or 0x000 respectively.
Fix/Workaround
Write the desired value added by two to the DFLL0CONF.FINE field.
The BODVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
BRIFA is non-functional.
Fix/Workaround
None.
VREGCR.DEEPMODEDISABLE bit is not readable.
Fix/Workaround
None.
AT32UC3L016/32/64
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