AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 475

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 21-9. Master Read with Multiple Data Bytes
21.8.5
21.8.5.1
32099F–11/2010
SR.IDLE
RXRDY
TWD
Using the Peripheral DMA Controller
NBYTES set to m
Write START +
Data Transmit with the Peripheral DMA Controller
S
STOP bit
DADR
Programming CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with
no data bytes, ie START, DADR+R, STOP
The TWI transfers require the master to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the
master to pull it down in order to generate the acknowledge. All data bytes except the last are
acknowledged by the master. Not acknowledging the last byte informs the slave that the trans-
fer is finished.
RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.
Figure 21-8. Master Read with One Data Byte
The use of the Peripheral DMA Controller significantly reduces the CPU load. The program-
mer can set up ring buffers for the DMA controller, containing data to transmit or free buffer
space to place received data.
To assure correct behavior, respect the following programming sequences:
1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
R
A
SR.IDLE
RXRDY
TWD
DATAn
NBYTES set to 1
Write START &
S
STOP bit
Read RHR
DADR
DATAn
A
DATAn+1
R
DATAn+m-2
Read RHR
A
DATAn+m-1
DATA
AT32UC3L016/32/64
DATAn+m-1
Read RHR
A
N
Read RHR
DATAn+m
When NBYTES=0
P
Send STOP
N
Read RHR
DATAn+m
P
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