AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 702
AT32UC3L-EK
Manufacturer Part Number
AT32UC3L-EK
Description
KIT EVAL AVR32 UC3 MCU
Manufacturer
Atmel
Type
MCUr
Specifications of AT32UC3L-EK
Contents
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
UC3L
Kit Contents
Board
Features
USB / Battery Powered, Board Controller / Bootloader
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Tool Type
Starter Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor Series
AT32
Processor To Be Evaluated
AT32UC3L064
Interface Type
USB, Capacitive Touch
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L-EK
Manufacturer:
Atmel
Quantity:
135
- Current page: 702 of 858
- Download datasheet (13Mb)
29.4
29.5
29.5.1
29.5.2
29.5.3
29.6
29.6.1
32099F–11/2010
I/O Lines Description
Product Dependencies
Functional Description
I/O Lines
Clocks
Debug Operation
Enabling the Lookup Table Inputs
Table 29-1.
Each LUT have 4 inputs and one output. The inputs and outputs for the LUTs are mapped
sequentially to the inputs and outputs. This means that LUT0 is connected to IN0 to IN3 and
OUT0. LUT1 is connected to IN4 to IN7 and OUT1. In general, LUTn is connected to IN[4n] to
IN[4n+3] and OUTn.
In order to use this module, other parts of the system must be configured correctly, as described
below.
The pins used for interfacing the GLOC may be multiplexed with I/O Controller lines. The pro-
grammer must first program the I/O Controller to assign the desired GLOC pins to their
peripheral function. If I/O lines of the GLOC are not used by the application, they can be used for
other purposes by the I/O Controller.
It is only required to enable the GLOC inputs and outputs actually in use. Pullups for pins config-
ured to be used by the GLOC will be disabled.
The clock for the GLOC bus interface (CLK_GLOC) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the GLOC before disabling the clock, to avoid freezing the module in an undefined state.
Additionally, the GLOC depends on a dedicated Generic Clock (GCLK). The GCLK can be set to
a wide range of frequencies and clock sources, and must be enabled by the System Control
Interface (SCIF) before the GLOC filter can be used.
When an external debugger forces the CPU into debug mode, the GLOC continues normal
operation.
Since the inputs to each lookup table (LUT) unit can be multiplexed with other peripherals, each
input must be explicitly enabled by writing a one to the corresponding enable bit (AEN) in the
corresponding Control Register (CR).
If no inputs are enabled, the output OUTn will be the least significant bit in the TRUTHn register.
Pin Name
IN0-INm
OUT0-OUTn
I/O Lines Description
Output from lookup tables
Pin Description
Inputs to lookup tables
AT32UC3L016/32/64
Type
Input
Output
702
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