AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 804

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

32.10 Timing Characteristics
32.10.1
Table 32-36. Maximum Reset and Wake-up Timing
Note:
32.10.2
Table 32-37. RESET_N Waveform Parameters
Note:
32099F–11/2010
Parameter
Startup time from power-up, using
regulator
Startup time from power-up, no
regulator
Startup time from reset release
Wake-up
Wake-up from shutdown
Symbol
t
RESET
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
Startup, Reset, and Wake-up Timing
RESET_N Timing
cess technology. These values are not covered by test limits in production.
cess technology. These values are not covered by test limits in production.
Parameter
RESET_N minimum pulse length
Idle
Frozen
Standby
Stop
Deepstop
Static
The startup, reset, and wake-up timings are calculated using the following formula:
Where
another clock source than RCSYS is selected as CPU clock the startup time of the oscillator,
Please refer to the source for the CPU clock in the
more details about oscillator startup times.
t
t
OSCSTART
=
t
CONST
t
CONST
Time from VDDIN crossing the V
POR33 to the first instruction entering the decode
stage of CPU. VDDCORE is supplied by the internal
regulator.
Time from VDDIN crossing the V
POR33 to the first instruction entering the decode
stage of CPU. VDDCORE is connected to VDDIN.
Time from releasing a reset source (except POR18,
POR33, and SM33) to the first instruction entering
the decode stage of CPU.
From wake-up event to the first instruction of an
interrupt routine entering the decode stage of the
CPU.
From wake-up event to the first instruction entering
the decode stage of the CPU.
Measuring
, must added to the wake-up time in the stop, deepstop, and static sleep modes.
+
N
and
CPU
N
×
(1)
CPU
t
CPU
(1)
are found in
Conditions
POT+
POT+
Table
threshold of
threshold of
32-36.
”Oscillator Characteristics” on page 791
t
CPU
AT32UC3L016/32/64
Min
10
Max
is the period of the CPU clock. If
27 +
27 +
97 +
t
CONST
t
t
t
2210
1810
1180
OSCSTART
OSCSTART
OSCSTART
170
0
0
0
Max
(in µs)
Units
ns
Max
110
110
116
116
116
N
19
0
0
0
0
CPU
804
for