AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 822

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

35.1.8
35.1.9
32099F–11/2010
SPI
TWI
1. SPI disable does not work in SLAVE mode
2. SPI Bad serial clock generation on 2nd chip select when SCBR==1, CPOL==1, and
3. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
4. Disabling SPI has no effect on the SR.TDRE bit
5. SPI mode fault detection enable causes incorrect behavior
1. TWIM.SR.IDLE goes high immediately when NAK is received
Fix / Workaround
Disable the interrupt, clear the interrupt by writing a one to GPIO.IFRC, then enable the
interrupt.
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
NCPHA==0
W h e n m u l t i p l e c h i p s e l e c t s a r e i n u s e , i f o n e o f t h e b a u d r a t e s i s e q u a l t o 1
(CSRn.SCBR==1) and one of the others is not equal to 1, and CSRn.CPOL==1 and
CSRn.NCPHA==0, an additional pulse will be generated on SCK.
Fix/Workaround
When multiple chip selects are in use, if one of the baudrates is equal to 1, the others must
also be equal to 1 if CSRn.CPOL==1 and CSRn.NCPHA==0.
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
Disabling SPI has no effect on SR.TDRE whereas the write data command is filtered when
SPI is disabled. This means that as soon as the SPI is disabled it becomes impossible to
reset the SR.TDRE bit by writing to TDR. So if the SPI is disabled during a PDCA transfer,
the PDCA will continue to write data to TDR (as SR.TDRE stays high) until its buffer is
empty, and all data written after the disable command is lost.
Fix/Workaround
Disable the PDCA, add 2 NOP (minimum), and disable the SPI. To continue the transfer,
enable the SPI and the PDCA.
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
properly.
Fix/Workaround
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
AT32UC3L016/32/64
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