AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 429

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.7.2
Figure 20-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
32099F–11/2010
SPCK cycle (for reference)
Data Transfer
(from master)
(from slave)
(CPOL = 0)
(CPOL = 1)
(to slave)
SPCK
SPCK
MOSI
MISO
NSS
Four combinations of polarity and phase are available for data transfers. The clock polarity is
configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock
phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two
bits determine the edges of the clock signal on which data is driven and sampled. Each of the
two bits has two possible states, resulting in four possible combinations that are incompatible
with one another. Thus, a master/slave pair must use the same parameter pair values to com-
municate. If multiple slaves are used and fixed in different configurations, the master must
reconfigure itself each time it needs to communicate with a different slave.
Table 20-2 on page 429
Table 20-2.
Figure 20-3 on page 429
MSB
1
MSB
*** Not Defined, but normaly MSB of previous character received
SPI modes
2
6
6
SPI Mode
0
1
2
3
3
shows the four modes and corresponding parameter settings.
and
5
5
Figure 20-4 on page 430
4
4
4
5
3
3
6
2
2
show examples of data transfers.
7
AT32UC3L016/32/64
CPOL
1
1
0
0
1
1
8
LSB
LSB
***
NCPHA
1
0
1
0
429