AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 403
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
AT32UC3L-EK
Manufacturer Part Number
AT32UC3L-EK
Description
KIT EVAL AVR32 UC3 MCU
Manufacturer
Atmel
Type
MCUr
Specifications of AT32UC3L-EK
Contents
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
UC3L
Kit Contents
Board
Features
USB / Battery Powered, Board Controller / Bootloader
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Tool Type
Starter Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor Series
AT32
Processor To Be Evaluated
AT32UC3L064
Interface Type
USB, Capacitive Touch
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L-EK
Manufacturer:
Atmel
Quantity:
135
- Current page: 403 of 858
- Download datasheet (13Mb)
19.7.1
Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
•
•
•
32099F–11/2010
LINWKUP: Send LIN Wakeup Signal
LINABT: Abort LIN Transmission
RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select
RTSEN/FCS: Request to Send Enable/Force SPI Chip Select
RETTO: Rearm Time-out
RSTNACK: Reset Non Acknowledge
RSTIT: Reset Iterations
RETTO
TXDIS
31
23
15
–
–
7
0: No effect:
1: Sends a wakeup signal on the LIN bus.
0: No effect.
1: Abort the current LIN transmission.
If USART does not operate in SPI Master Mode (MODE … 0xE):
0: No effect.
1: Drives the pin RTS to 1.
If USART operates in SPI Master Mode (MODE = 0xE):
RCS = 0: No effect.
RCS = 1: Releases the Slave Select Line NSS (RTS pin).
If USART does not operate in SPI Master Mode (MODE … 0xE):
0: No effect.
1: Drives the pin RTS to 0.
If USART operates in SPI Master Mode (MODE = 0xE):
FCS = 0: No effect.
FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave
devices supporting the CSAAT Mode (Chip Select Active After Transfer).
0: No effect
1: Restart Time-out
0: No effect
1: Resets NACK in CSR.
0: No effect.
1: Resets ITERATION in CSR.
Control Register
RSTNACK
TXEN
30
22
14
CR
Write-only
0x0
-
–
–
6
LINWKUP
RXDIS
RSTIT
29
21
13
–
5
LINABT
SENDA
RXEN
28
20
12
–
4
RTSDIS/RCS
STTTO
RSTTX
27
19
11
–
3
RTSEN/FCS
STPBRK
RSTRX
26
18
10
–
2
AT32UC3L016/32/64
STTBRK
25
17
–
–
9
1
–
RSTSTA
24
16
–
–
8
0
–
403
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