AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 638

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.6.1.1
27.6.1.2
27.6.1.3
27.6.1.4
27.6.2
27.6.3
32099F–11/2010
Interrupt Generation
Peripheral Event Generation
Continuous Measurement Mode
User Triggered Single Measurement Mode
Event Triggered Single Measurement Mode
Selecting Comparator Inputs
In CM, the Analog Comparator is continuously enabled and performing comparisons. This
ensures that the result of the latest comparison is always available in the ACn Current Compari-
son Status bit in the Status Register (SR.ACCSn). Comparisons are done on every positive
edge of GCLK.
CM is enabled by writing CONFn.MODE to 1. After the startup time has passed, a comparison is
done and SR is updated. Appropriate peripheral events and interrupts are also generated. New
comparisons are performed continuously until the CONFn.MODE field is written to 0.
In the UT mode, the user starts a single comparison by writing a one to the User Start Single
Comparison bit (CTRL.USTART). This mode is enabled by writing CONFn.MODE to 2. After the
startup time has passed, a single comparison is done and SR is updated. Appropriate peripheral
events and interrupts are also generated. No new comparisons will be performed.
CTRL.USTART is cleared automatically by hardware when the single comparison has been
done.
This mode is enabled by writing CONFn.MODE to 3 and Peripheral Event Trigger Enable
(CTRL.EVENTEN) to one. The ET mode is similar to the UT mode, the difference is that a
peripheral event from another hardware module causes the hardware to automatically set the
Peripheral Event Start Single Comparison bit (CTRL.ESTART). After the startup time has
passed, a single comparison is done and SR is updated. Appropriate peripheral events and
interrupts are also generated. No new comparisons will be performed. CTRL.ESTART is cleared
automatically by hardware when the single comparison has been done.
Each Analog Comparator has one positive (INP) and one negative (INN) input. The positive
input is fed from an external input pin (ACPn). The negative input can either be fed from an
external input pin (ACNn) or from a reference voltage common to all ACs (ACREFN).
The user selects the input source as follows:
The interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in ISR is cleared
by writing a one to the corresponding bit in the Interrupt Status Clear Register (ICR).
The ACIFB can be set up so that certain comparison results notify other parts of the device via
the Peripheral Event system. Refer to
which comparison results can generate events, and how to configure the ACIFB to achieve this.
• In normal mode with the Negative Input Select and Positive Input Select fields
• In window mode with CONFn.INSELN, CONFn.INSELP and CONFn+1.INSELN,
(CONFn.INSELN and CONFn.INSELP).
CONFn+1,INSELP. The user must configure CONFn.INSELN and CONFn+1.INSELP to the
same source.
Section 27.6.4.3
and
AT32UC3L016/32/64
Section 27.6.5.3
for information on
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