AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 512

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.8.8
32099F–11/2010
Identifying Bus Events
This chapter lists the different bus events, and how these affects bits in the TWIS registers.
This is intended to help writing drivers for the TWIS.
Table 22-5.
Event
Slave transmitter has sent a
data byte
Slave receiver has received
a data byte
Start+Sadr on bus, but
address is to another slave
Start+Sadr on bus, current
slave is addressed, but
address match enable bit in
CR is not set
Start+Sadr on bus, current
slave is addressed,
corresponding address
match enable bit in CR set
Start+Sadr on bus, current
slave is addressed,
corresponding address
match enable bit in CR set,
SR.STREN and SR.SOAM
are set.
Repeated Start received
after being addressed
Stop received after being
addressed
Start, Repeated Start or
Stop received in illegal
position on bus
Data is to be received in
slave receiver mode,
SR.STREN is set, and RHR
is full
Data is to be transmitted in
slave receiver mode,
SR.STREN is set, and THR
is empty
Data is to be received in
slave receiver mode,
SR.STREN is cleared, and
RHR is full
Bus Events
Effect
SR.THR is cleared.
SR.BTF is set.
The value of the ACK bit sent immediately after the data byte is given
by CR.ACK.
SR.RHR is set.
SR.BTF is set.
SR.NAK updated according to value of ACK bit received from master.
None.
None.
Correct address match bit in SR is set.
SR.TRA updated according to transfer direction.
Slave enters appropriate transfer direction mode and data transfer
can commence.
Correct address match bit in SR is set.
SR.TRA updated according to transfer direction.
Slave stretches TWCK immediately after transmitting the address
ACK bit. TWCK remains stretched until all address match bits in SR
have been cleared.
Slave the enters appropriate transfer direction mode and data transfer
can commence.
SR.REP set.
SR.TCOMP unchanged.
SR.STO set.
SR.TCOMP set.
SR.BUSERR set.
TWCK is stretched until RHR has been read.
TWCK is stretched until THR has been written.
TWCK is not stretched, read data is discarded.
SR.ORUN is set.
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