AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 137

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.6
10.6.1
32099F–11/2010
Module Configuration
Bus Matrix Connections
The specific configuration for each HMATRIX instance is listed in the following tables.The mod-
ule bus clocks listed here are connected to the system bus clocks. Please refer to the Power
Manager chapter for details.
Table 10-3.
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0
register is associated with the CPU Data master interface.
Table 10-4.
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is
associated with the Internal SRAM Slave Interface.
Accesses to unused areas returns an error result to the master requesting such an access.
Table 10-5.
Clock Name
CLK_HMATRIX
Master 0
Master 1
Master 2
Master 3
Master 4
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
HMATRIX Clocks
High Speed Bus Masters
High Speed Bus Slaves
CPU Data
CPU Instruction
CPU SAB
SAU
PDCA
Internal Flash
HSB-PB Bridge A
HSB-PB Bridge B
Internal SRAM
SAU
Description
Clock for the HMATRIX bus interface
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