AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 522
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AT32UC3L-EK
Manufacturer Part Number
AT32UC3L-EK
Description
KIT EVAL AVR32 UC3 MCU
Manufacturer
Atmel
Type
MCUr
Specifications of AT32UC3L-EK
Contents
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
UC3L
Kit Contents
Board
Features
USB / Battery Powered, Board Controller / Bootloader
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Tool Type
Starter Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor Series
AT32
Processor To Be Evaluated
AT32UC3L064
Interface Type
USB, Capacitive Touch
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L-EK
Manufacturer:
Atmel
Quantity:
135
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22.9.7
Name:
Access Type:
Offset:
Reset Value:
• BTF: Byte Transfer Finished
• REP: Repeated Start Received
• STO: Stop Received
• SMBDAM: SMBus Default Address Match
• SMBHHM: SMBus Host Header Address Match
• SMBALERTM: SMBus Alert Response Address Match
• GCM: General Call Match
• SAM: Slave Address Match
• BUSERR: Bus Error
32099F–11/2010
ORUN
BTF
31
23
15
7
-
This bit is set when byte transfer has completed.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when REPEATED START condition received.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when STOP condition received.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when received address matched SMBus Default Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when received address matched SMBus Host Header Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when received address matched SMBus Alert Response Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when received address matched General Call Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when received address matched Slave Address.
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a misplaced start or stop condition has occurred.
This bit is cleared when the corresponding bit in SCR is written to one.
Status Register
BUSERR
URUN
REP
30
22
14
6
SR
Read-only
0x18
0x000000002
SMBPECERR
STO
TRA
29
21
13
5
SMBTOUT
SMBDAM
28
20
12
4
-
-
SMBHHM
TCOMP
27
19
11
3
-
SMBALERTM
SEN
26
18
10
2
-
AT32UC3L016/32/64
TXRDY
GCM
25
17
9
1
-
RXRDY
SAM
NAK
24
16
8
0
522
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