AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 467

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21. Two-Wire Master Interface (TWIM)
21.1
21.2
32099F–11/2010
Features
Overview
Rev 1.0.1.1
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The Atmel Two-wire Interface Master (TWIM) interconnects components on a unique two-wire
bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial
EEPROM and I²C compatible device such as a real rime clock (RTC), dot matrix/graphic LCD
controller and temperature sensor, to name a few. TWIM is always a bus master and can
transfer sequential or single bytes. Multiple master capability is supported. Arbitration of the
bus is performed internally and relinquishes the bus automatically if the bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range
of core clock frequencies.
wire Interface in Master Mode and a full I²C compatible device.
Table 21-1.
Note:
I²C
Standard Mode Speed (100 KHz)
Fast Mode Speed (400 KHz)
7- or 10-bits Slave Addressing
START BYTE
Repeated Start (Sr) Condition
ACK and NACK Management
Slope Control and Input Filtering (Fast mode)
Clock Stretching
Compatible with I
Compatible with SMBus standard
Compatible with PMBus
Compatible with Atmel Two-Wire Interface Serial Memories
DMA interface for reducing CPU load
Arbitrary transfer lengths, including 0 data bytes
Optional clock stretching if transmit or receive buffers not ready for data transfer
– Multi-master support
– 100 and 400 kbit/s transfer speeds
– 7- and 10-bit and General Call addressing
– Hardware Packet Error Checking (CRC) generation and verification with ACK control
– SMBus ALERT interface
– 25 ms clock low timeout delay
– 10 ms master cumulative clock low extend time
– 25 ms slave cumulative clock low extend time
Standard
1. START + b000000001 + Ack + Sr
(1)
Atmel TWIM Compatibility with I²C Standard
²
C standard
Table 21-1 on page 467
Atmel TWIM
Supported
Supported
Supported
Not Supported
Supported
Supported
Supported
Supported
lists the compatibility level of the Atmel Two-
AT32UC3L016/32/64
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