AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 583

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.7.8
Name:
Access Type:
Offset:
Reset Value:
Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
• MTIOB: TIOB Mirror
• MTIOA: TIOA Mirror
• CLKSTA: Clock Enabling Status
• ETRGS: External Trigger Status
• LDRBS: RB Loading Status
• LDRAS: RA Loading Status
• CPCS: RC Compare Status
32099F–11/2010
ETRGS
31
23
15
7
-
-
-
1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven
high.
0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven
low.
1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven
high.
0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven
low.
1: This bit is set when the clock is enabled.
0: This bit is cleared when the clock is disabled.
1: This bit is set when an external trigger has occurred.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RC Compare has occurred.
0: This bit is cleared when the SR register is read.
Channel Status Register
LDRBS
30
22
14
6
-
-
-
SR
Read-only
0x20 + n * 0x40
0x00000000
LDRAS
29
21
13
5
-
-
-
CPCS
28
20
12
4
-
-
-
CPBS
27
19
11
3
-
-
-
MTIOB
CPAS
26
18
10
2
-
-
AT32UC3L016/32/64
LOVRS
MTIOA
25
17
9
1
-
-
CLKSTA
COVFS
24
16
8
0
-
-
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