AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 61

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.7.17
Name:
Access Type:
Offset:
Reset Value:
• MON1CH: Performance Monitor Channel 1
• MON0CH: Performance Monitor Channel 0
• CH1RES: Performance Channel 1 Counter Reset
• CH0RES: Performance Channel 0 Counter Reset
• CH1OF: Performance Channel 1 Overflow Freeze
• CH1OF: Performance Channel 0 Overflow Freeze
• CH1EN: Performance Channel 1 Enable
• CH0EN: Performance Channel 0 Enable
32099F–11/2010
31
23
15
7
-
-
-
-
The PDCA channel number to monitor with counter n
Due to performance monitor hardware resource sharing, the two performance monitor channels should NOT be programmed to
monitor the same PDCA channel. This may result in UNDEFINED monitor behavior.
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in performance channel 1.
This bit always reads as zero.
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in performance channel 0.
This bit always reads as zero.
0: The performance channel registers are reset if DATA or STALL overflows.
1: All performance channel registers are frozen just before DATA or STALL overflows.
0: The performance channel registers are reset if DATA or STALL overflows.
1: All performance channel registers are frozen just before DATA or STALL overflows.
0: Performance channel 1 is disabled.
1: Performance channel 1 is enabled.
0: Performance channel 0 is disabled.
1: Performance channel 0 is enabled.
Performance Control Register
30
22
14
6
-
-
-
-
PCONTROL
Read/Write
0x800
0x00000000
CH1OF
29
21
13
5
-
CH0OF
28
20
12
4
-
27
19
11
3
-
-
MON1CH
MON0CH
26
18
10
2
-
-
AT32UC3L016/32/64
CH1RES
CH1EN
25
17
9
1
CH0RES
CH0EN
24
16
8
0
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