AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 32
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AT32UC3L-EK
Manufacturer Part Number
AT32UC3L-EK
Description
KIT EVAL AVR32 UC3 MCU
Manufacturer
Atmel
Type
MCUr
Specifications of AT32UC3L-EK
Contents
*
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
UC3L
Kit Contents
Board
Features
USB / Battery Powered, Board Controller / Bootloader
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
Tool Type
Starter Kit
Cpu Core
AVR 8
Data Bus Width
8 bit
Processor Series
AT32
Processor To Be Evaluated
AT32UC3L064
Interface Type
USB, Capacitive Touch
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L-EK
Manufacturer:
Atmel
Quantity:
135
- Current page: 32 of 858
- Download datasheet (13Mb)
5. Memories
5.1
5.2
Table 5-2.
32099F–11/2010
Embedded Memories
Physical Memory Map
AT32UC3L064
AT32UC3L032
AT32UC3L016
Part Number
Flash Memory Parameters
•
•
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented
translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space
is mapped as follows:
Table 5-1.
Device
Embedded SRAM
Embedded Flash
HSB-PB Bridge B
HSB-PB Bridge A
Internal High-Speed Flash
Internal High-Speed SRAM, Single-cycle access at full speed
– 64Kbytes (AT32UC3L064)
– 32Kbytes (AT32UC3L032)
– 16Kbytes (AT32UC3L016)
– 16Kbytes (AT32UC3L064, AT32UC3L032)
– 8Kbytes (AT32UC3L016)
• 0 Wait State Access at up to 25MHz in Worst Case Conditions
• 1 Wait State Access at up to 50MHz in Worst Case Conditions
• Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding
• Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation
• 100 000 Write Cycles, 15-year Data Retention Capability
• Sector Lock Capabilities, Bootloader Protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User Page For Data To Be Preserved During Chip Erase
penalty of 1 wait state access
to only 8% compared to 0 wait state operation
Flash Size (FLASH_PW)
AT32UC3L Physical Memory Map
64Kbytes
32Kbytes
16Kbytes
Start Address
0x00000000
0x80000000
0xFFFE0000
0xFFFF0000
Size
AT32UC3L064
64Kbytes
64Kbytes
64Kbytes
16Kbytes
Number of pages
(FLASH_P)
256
128
64
AT32UC3L032
16Kbytes
32Kbytes
64Kbytes
64Kbytes
AT32UC3L016/32/64
AT32UC3L016
8Kbytes
16Kbytes
64Kbytes
64Kbytes
(FLASH_W)
Page size
256 bytes
256 bytes
256 bytes
32
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