AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 384

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 19-23. Slave Node Synchronization
32099F–11/2010
Fractional Part (FP)
Clcok Divider (CD)
Synchro Counter
Baud Rate
LINIDRX
BRGR
BRGR
Clock
RXD
When the start bit of the Synch Field is detected the counter is reset. Then during the next 8
Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is
stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) gives the
new clock divider (CD) and the 3 least significant bits of this value (the remainder) gives the new
fractional part (FP).
When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are
updated in the Baud Rate Generator register (BRGR).
The accuracy of the synchronization depends on several parameters:
The following formula is used to compute the deviation of the slave bit rate relative to the master
bit rate after synchronization (F
F
LIN Standard imposes that it must not exceed ±15%. The LIN Standard imposes also that for
communication between two nodes, their bit rate must not differ by more than ±2%. This means
that the Baudrate_deviation must not exceed ±1%.
It follows from that, a minimum value for the nominal clock frequency:
TOL_UNSYNCH
• The nominal clock frequency (F
• The Baudrate
• The oversampling (Over=0 => 16X or Over=0 => 8X)
13 dominant bits (at 0)
Break Field
is the deviation of the real slave node clock from the nominal clock frequency. The
Baudrate_deviation
Baudrate_deviation
Initial CD
Initial FP
1 recessive bit
Delimiter
Break
(at 1)
Reset
SLAVE
Start
Bit
Nom
=
=
is the real slave node clock frequency).
1
⎛
⎝
⎛
⎜
⎜
⎜
⎝
) (the theoretical slave node clock frequency)
100
100
–
0
0,5
Synch Byte = 0x55
1
×
×
≤
α [
-------------------------------------------------------------------------------------------- -
α [
-------------------------------------------------------------------------------------------- -
0
α +0,5
≤
×
×
1
8
8
8
×
0
×
×
⎛
⎝
(
(
F
-------------------------------------- -
1
2 Over
2 Over
TOL_UNSYNCH
–
–
0
8
-1
AT32UC3L016/32/64
000_0011_0001_0110_1101
Stop
×
100
Bit
<
0000_0110_0010_1101
101
F
β
Start
SLAVE
Bit
)
)
<
+ ]
+ ]
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
+1
β
β
⎞ xF
⎠
×
×
Baudrate
Baudrate
Nom
⎞ %
⎠
⎞
⎟
⎟
⎟
⎠
%
Stop
Bit
384