AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 555

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.5.2
24.5.3
24.5.4
24.5.5
24.5.6
24.6
24.6.1
24.6.1.1
24.6.1.2
32099F–11/2010
Functional Description
Power Management
Clocks
Interrupts
Peripheral Events
Debug Operation
TC Description
Channel I/O Signals
16-bit counter
When using the TIOA lines as inputs the user must make sure that no peripheral events are gen-
erated on the line. Refer to the Peripheral Event System chapter for details.
If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning
and resume operation after the system wakes up from sleep mode.
The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
TC before disabling the clock, to avoid freezing the TC in an undefined state.
The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt
requires the interrupt controller to be programmed first.
The TC peripheral events are connected via the Peripheral Event System. Refer to the Periph-
eral Event System chapter for details.
The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps
peripherals running in debug operation.
The three channels of the Timer Counter are independent and identical in operation. The regis-
ters for channel programming are listed in
As described in
Table 24-2.
Each channel is organized around a 16-bit counter. The value of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF and
passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Sta-
tus Register (SRn.COVFS) is set.
Block/Channel
Channel Signal
Channel I/O Signals Description
Figure 24-1 on page
XC0, XC1, XC2
Signal Name
SYNC
TIOA
TIOB
INT
554, each Channel has the following I/O signals.
Figure 24-3 on page
Description
External Clock Inputs
Capture mode: Timer Counter Input
Waveform mode: Timer Counter Output
Capture mode: Timer Counter Input
Waveform mode: Timer Counter Input/Output
Interrupt Signal Output
Synchronization Input Signal
AT32UC3L016/32/64
570.
555