AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 156

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.6.4.2
32099F–11/2010
Entering Shutdown sleep mode
The table gives the possible usage of the I/O lines that stay powered during the Shutdown sleep
mode. If no special function are used, then the I/O lines will keep its settings before entering the
sleep mode
Table 12-3.
Before entering the Shutdown sleep mode, a few actions are required:
.
As soon as the Shutdown sleep mode is entered, all CPU and peripherals are reset to ensure a
consistent state.
POR33 and RC32K oscillator are automatically disabled when entering the Shutdown sleep
mode to save extra power
Pin
PA11
PA13
PA20
PA21
PB04
PB05
PB10
RESET_N
– AST core logic (internal counter and alarm detection logic)
– Backup Registers
– I/O lines PA11, PA13, PA20, PA21, PB04, PB05, PB10
– RESET_N line
– All modules should normally be disabled before entering Shutdown sleep mode (see
– The POR33 (see System Control Interface “SCIF” chapter) must be masked to avoid
– The 32KHz RC oscillator (RC32K) must be running and stable. This is done by
Section
any spurious reset when the power is back. This is done by writing a one to the
POR33MASK bit of the SCIF.VREGCR register. Because of internal
synchronisation, this bit must be read as a one before the sleep instruction is
executed by the CPU.
writing a one to the EN bit of the SCIF.RC32KCR register. Because of internal
synchronisation, this bit must be read as a one to ensure that the oscillator is stable
before the sleep instruction is executed by the CPU
I/O Lines Usage During Shutdown Mode
12.6.3.4)
Possible Usage During Shutdown Sleep Mode
XIN32_2 (2nd 32KHz crystal oscillator)
WAKE_N signal (active low wake-up)
XOUT32_2
Reset pin
AT32UC3L016/32/64
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