AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 472

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.8.2.1
21.8.2.2
32099F–11/2010
Clock Generation
Setting up and Performing a Transfer
The Clock Waveform Generator Register (CWGR) is used to control the waveform of the
TWCK clock. CWGR must be programmed so that the desired TWI bus timings are generated.
CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescal-
ing can be selected through the EXP field in CWGR.
CWGR has the following fields:
LOW: Prescaled clock cycles in clock low count. Used to time T
HIGH: Prescaled clock cycles in clock high count. Used to time T
STASTO: Prescaled clock cycles in clock high count. Used to time T
DATA: Prescaled clock cycles for data setup and hold count. Used to time T
EXP: Specifies the clock prescaler setting.
Note that the total clock low time generated is the sum of T
Any slave or other bus master taking part in the transfer may extend the TWCK low period at
any time.
The TWIM hardware monitors the state of the TWCK line as required by the I²C specification.
The clock generation counters are started when a high/low level is detected on the TWCK line,
not when the TWIM hardware releases/drives the TWCK line. This means that the CWGR set-
tings alone do not determine the TWCK frequency. The CWGR settings determine the clock
low time and the clock high time, but the TWCK rise and fall times are determined by the exter-
nal circuitry (capacitive load, etc.).
Figure 21-5. Bus Timing Diagram
Operation of TWIM is mainly controlled by the Control Register (CR) and the Command Reg-
ister (CMDR). The following list presents the main steps in a typical communication:
f
prescaled
S
=
t
t LOW
HD:STA
-------------------------
2
(
EXP
f
clkpb
+ )
1
t
SU:DAT
)
t HIGH
t
HD:DAT
t LOW
t
t
SU:DAT
SU:STA
AT32UC3L016/32/64
HD_DAT
Sr
LOW
HIGH
+ T
. and T
HD_STA
.
SU_DAT
BUF
, T
t
HD_DAT
+ T
SU:STO
SU_STA
.
LOW
, T
.
, T
SU_DAT
P
SU_STO
472
.
.