AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 777

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

31.6.7.11
31.6.7.12
31.6.7.13
32099F–11/2010
HALT
RESET
SET_GUARD_TIME
This command tells the CPU to halt code execution for safe programming. If the CPU is not
halted during programming it can start executing partially loaded programs. To halt the proces-
sor, the aWire master should send 0x01 in the data field of the command. After programming the
halting can be released by sending 0x00 in the data field of the command.
Table 31-46. HALT Details
This command resets different domains in the part. The aWire master sends a byte with the
reset value. Each bit in the reset value byte corresponds to a reset domain in the chip. If a bit is
set the reset is activated and if a bit is not set the reset is released. The number of reset domains
and their destinations are identical to the resets described in the JTAG data registers chapter
under reset register.
Table 31-47. RESET Details
Sets the guard time value in the AW, i.e. how long the AW will wait before starting its transfer
after the master has finished.
The guard time can be either 0x00 (128 bit lengths), 0x01 (16 bit lengths), 0x2 (4 bit lengths) or
0x3 (1 bit length).
Table 31-48. SET_GUARD_TIME Details
Command
Command value
Additional data
Possible responses
Command
Command value
Additional data
Possible responses
Command
Command value
Additional data
Possible responses
Details
0x82
0x01 to halt the CPU 0x00 to release the halt and reset the
device.
0x40: ACK
0x41: NACK
Details
0x83
Reset value for each reset domain. The number of reset
domains is part specific.
0x40: ACK
0x41: NACK
Details
0x84
Guard time
0x40: ACK
0x41: NACK
(Section
(Section
(Section
(Section
(Section
(Section
31.6.8.1)
31.6.8.1)
31.6.8.1)
AT32UC3L016/32/64
31.6.8.2)
31.6.8.2)
31.6.8.2)
777