AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 405

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.7.2
Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
•
•
•
32099F–11/2010
FILTER: Infrared Receive Line Filter
DSNACK: Disable Successive NACK
INACK: Inhibit Non Acknowledge
OVER: Oversampling Mode
CLKO: Clock Output Select
MODE9: 9-bit Character Length
MSBF/CPOL: Bit Order or SPI Clock Polarity
31
23
15
–
–
7
0: The USART does not filter the receive line.
1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a
NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is
asserted.
0: The NACK is generated.
1: The NACK is not generated.
0: 16x Oversampling.
1: 8x Oversampling.
0: The USART does not drive the CLK pin.
1: The USART drives the CLK pin if USCLKS does not select the external clock CLK.
0: CHRL defines character length.
1: 9-bit character length.
If USART does not operate in SPI Mode (MODE … 0xE and 0xF):
MSBF = 0: Least Significant Bit is sent/received first.
MSBF = 1: Most Significant Bit is sent/received first.
If USART operates in SPI Mode (Slave or Master, MODE = 0xE or 0xF):
CPOL = 0: The inactive state value of SPCK is logic level zero.
CPOL = 1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required
clock/data relationship between master and slave devices.
Mode Register
CHMODE
CHRL
30
22
14
MR
Read-write
0x4
-
–
–
6
DSNACK
29
21
13
–
5
NBSTOP
USCLKS
FILTER
INACK
28
20
12
4
OVER
27
19
11
–
3
CLKO
PAR
26
18
10
2
AT32UC3L016/32/64
MODE
MODE9
25
17
9
1
SYNC/CPHA
MSBF/CPOL
24
16
8
0
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