AT32UC3L-EK Atmel, AT32UC3L-EK Datasheet - Page 767

• Manufacturer Part Number: AT32UC3L-EK
• Description: KIT EVAL AVR32 UC3 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT32UC3L-EK

• Contents: *
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: UC3L
• Kit Contents: Board
• Features: USB / Battery Powered, Board Controller / Bootloader
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Tool Type: Starter Kit
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Processor Series: AT32
• Processor To Be Evaluated: AT32UC3L064
• Interface Type: USB, Capacitive Touch
• For Use With/related Products: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

31.6.5.1
31.6.5.2
31.6.5.3
31.6.5.4
31.6.6
31.6.6.1
Table 31-31. aWire Packet Format
32099F–11/2010
Field
COMMAND/
RESPONSE
SYNC
Functional Description
I/O Lines
Power Management
Clocks
External Components
aWire Communication Protocol
Number of bytes
1
1
The pin used by AW is multiplexed with the RESET_N pin. The reset functionality is the default
function of this pin. To enable the aWire functionality on the RESET_N pin the user must enable
the AW either by sending the enable sequence over the RESET_N pin from an external aWire
master or by enabling the aWire user interface.
In 2-pin mode data is received on the RESET_N line, but transmitted on the DATAOUT line.
After sending the 2_PIN_MODE command the DATAOUT line is automatically enabled. All other
peripheral functions on this pin is disabled.
When debugging through AW the system clocks are automatically turned on to allow debugging
in sleep modes.
The aWire UART uses the internal 120 MHz RC oscillator (RC120M) as clock source for its
operation. When enabling the AW the RC120M is automatically started.
The AW needs an external pullup on the RESET_N pin to ensure that the pin is pulled up when
the bus is not driven.
The AW is accessed through the RESET_N pin shown in
communicates through a UART operating at variable baud rate (depending on a sync pattern)
with one start bit, 8 data bits (LSB first), one stop bit, and no parity bits. The aWire protocol is
based upon command packets from an externalmaster and response packets from the slave
(AW). The master always initiates communication and decides the baud rate.
The packet contains a sync byte (0x55), a command/response byte, two length bytes (optional),
a number of data bytes as defined in the length field (optional), and two CRC bytes. If the com-
mand/response has the most significant bit set, the command/response also carries the optional
length and data fields. The CRC field is not checked if the CRC value transmitted is 0x0000.
Description
Sync pattern (0x55).
Command from the master or
response from the slave.
Comment
Used by the receiver to set the baud rate
clock.
When the most significant bit is set the
command/response has a length field. A
response has the next most significant bit
set. A command does not have this bit set.
AT32UC3L016/32/64
Table 31-30 on page
766. The AW
Optional
No
No
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