IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 134

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

8–4
Figure 8–2. Completed Design
Simulating the HDL Import Model using Simulink
DSP Builder Standard Blockset User Guide
12. Progress messages issue in the HDL Import dialog box ending with the message:
13. The HDL Import block in the MyFilter.mdl model updates to show the ports
14. Click OK to close the HDL Import dialog box.
15. Connect the input and output ports to the symbol
16. Click Save on the File menu to save the MyFilter.mdl file.
Follow these steps to run simulation in Simulink:
1. Double-click on the manual switch connected to the Tsamp block which feeds into
2. Click Start on the Simulation menu in your model window.
3. Double-click on the Scope block to view the simulation results.
4. Click the Autoscale icon to resize the scope. This scales both axes to display all
5. Click the Zoom X-axis icon and drag the cursor to zoom in on the first 70 X-axis
Quartus II Analysis & Synthesis was successful.
defined in the imported HDL.
generated for the HDL Import block automatically converts to a black box.
the fir_data_in input port.
This toggles the switch and sets the impulse_in stimulus, which verifies the
impulse response of the low-pass filter.
stored simulation data until the end of the simulation (which is set to 500*Tsamp
for this model).
time units.
Figure 8–3 on page 8–5
shows the simulation results.
Preliminary
Chapter 8: Using Black Boxes for HDL Subsystems
(Figure
© June 2010 Altera Corporation
8–2). The code
HDL Import Design Example