IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 324

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–16
Non-synthesizable Output
Table 6–26. Non-synthesizable Output Block Parameters
Table 6–27. Non-synthesizable Output Block I/O Formats
DSP Builder Standard Blockset Libraries
Bus Type
[number of bits].[] >= 0 (Parameterizable)
[].[number of bits] >= 0 (Parameterizable)
External Type
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
I1
O1
[L].[R]
Name
[L1].[R1]
Simulink (2),
[LP].[RP]
Table
is an input port. O1
6–29:
Inferred, Signed Integer,
Unsigned Integer,
Signed Fractional,
Single Bit
Inferred,
Simulink Fixed Point Type,
Double
(3)
The Non-synthesizable Output block marks an exit point from a
non-synthesizable DSP Builder system. Use a corresponding
Input
Simulink, this block is required when the DSP Builder blocks are not intended to be
synthesized. You can also use this block to create an non-synthesizable output from a
synthesizable system.
You can optionally specify the external Simulink type. If set to Simulink Fixed
Point Type, the bit width is the same as the DSP Builder input type. If set to
Double, the width may be truncated if the bit width is greater than 52.
Table 6–26
Table 6–27
[L].[R]
I1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
is an output port.
Value
block to mark the entry point. Because DSP Builder registers its own type with
shows the Non-synthesizable Output block parameters.
shows the Non-synthesizable Output block I/O formats.
Specifies the number format of the bus.
Specifies the number of bits to the left of the binary point, including the
sign bit. This parameter does not apply to single-bit buses.
Specifies the number of bits to the right of the binary point. This
parameter applies only to signed fractional buses.
Specifies whether the external type is inferred from the Simulink block it
is connected to or explicitly set to either Simulink Fixed Point or Double
type. The default is Inferred.
Preliminary
(Note 1)
VHDL
Description
Non-synthesizable
© June 2010 Altera Corporation
Chapter 6: IO & Bus Library
Non-synthesizable Output
Implicit - Optional
Explicit
Type
(4)