IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 290

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–4
Table 5–1. Signals Supported by the Avalon-MM Master Block (Part 2 of 2)
Table 5–2. Avalon-MM Master Block Parameters (Part 1 of 2)
DSP Builder Standard Blockset Libraries
readdatavalid Input
flush
burstcount
irq
irqnumber
Specify Clock
Clock
Address Width
Address Type
Data Type
[number of bits].[]
[].[number of bits]
Allow Byte Enable
Allow Flow Control
Allow Pipeline
Transfers
Use Flush Signal
Allow Burst Transfers On or Off
Maximum Burst Size
Signal
Name
1
Output
Output
Input
Input
Direction
The direction in
interface.
Figure 5–2
On or Off
User defined
Read, Write,
Read/Write
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
On or Off
On or Off
On or Off
On or Off
2–32
1–32
Value
Available when Allow Pipeline Transfers is on. Use for pipelined read transfers with
latency. Indicates that valid data is present on the readdata lines.
Available when Allow Pipeline Transfers and Use Flush Signal are on. Can be asserted
to clear any pending transfers in the pipeline.
Available when Allow Burst Transfers is on. Indicates the number of transfers in a burst.
Available when Receive IRQ is on. Indicates when one or more ports have requested an
interrupt.
Available when Receive IRQ is on and IRQ mode is set to Prioritized. Indicates the
interrupt priority. Lower value means higher priority.
shows the Avalon-MM Master block parameters.
Table 5–1
Turn on to explicitly specify the clock name.
Specifies the clock signal name.
Specifies the number of address bits.
The address type for the bus.
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign
bit. Read and write buses must have the same number of bits.
Specifies the number of bits to the right of the binary point. This parameter
applies only to signed fractional buses.
Turn on to use the Byte Enable signal. This option is available when the
address type is set to Write or Read/Write and the bit width is greater than 8.
Turn on to enable flow control. Flow control allows a slave port to regulate
incoming transfers from a master port, so that a transfer only begins when the
slave port indicates that it has valid data or is ready to receive data.
Turn on to allow pipeline transfers. Pipeline transfers increase the bandwidth
for synchronous slave peripherals that require several cycles to return data for
the first access, but can return data every cycle thereafter. This option is
available when the address type is Read or Read/Write.
Turn on to clear any pending transfers in the pipeline. This option is available
when Allow Pipeline Transfers is on.
Turn on to allow burst transfers. A burst executes multiple transfers as a unit,
and maximize the throughput for slave ports that achieves the greatest
efficiency when handling multiple units of data from one master port at a time.
Specifies the maximum width of a burst transfer. This option is available when
Allow Burst Transfers is on.
refers to the direction in respect of the DSP Builder block
Preliminary
Description
Description
© June 2010 Altera Corporation
Chapter 5: Interfaces Library
Avalon-MM Master