IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 266

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–4
Table 4–5. Bitwise Logical Bus Operator Block Parameters
Table 4–6. Bitwise Logical Bus Operator Block I/O Formats
Figure 4–2. Bitwise Logical Bus Operator Block Example
DSP Builder Standard Blockset Libraries
Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Logic Operation
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2[
O1
[L].[R]
Name
[L1].[R1]
L1].[R1]
[L1].[R1]
Table
Simulink (2),
is an input port. O1
4–6:
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
AND, OR, XOR
Table 4–5
Table 4–6
Figure 4–2
(3)
[L].[R]
Value
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
shows the Bitwise Logical Bus Operator block parameters.
shows the Bitwise Logical Bus Operator block I/O formats.
shows an example with the Bitwise Logical Bus Operator block.
Specify the bus number format that you want to use.
Specify the number of bits to the left of the binary point, including the sign bit.
Specify the number of bits to the right of the binary point.
Specify the logical operation to perform.
Preliminary
(Note 1)
VHDL
Description
Chapter 4: Gate & Control Library
© June 2010 Altera Corporation
Bitwise Logical Bus Operator
Type
Explicit
Explicit
Explicit
(4)