IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 64

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–20
Hierarchical Design
Figure 3–19. Hierarchical Design Example
DSP Builder Standard Blockset User Guide
f
DSP Builder supports hierarchical design using the Simulink Subsystem block.
DSP Builder preserves the hierarchy structure in a VHDL design and each hierarchical
level in a Simulink model file (.mdl) translates into one VHDL file.
For example,
implements two FIR filters.
For information about naming the Subsystem block instances, refer to
Naming Conventions” on page
Figure 3–19
illustrates a hierarchy for a design fir3tap.mdl, which
Preliminary
3–1.
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
“DSP Builder
Hierarchical Design