IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 255

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Complex Type Library
Complex Delay
Complex Delay
Table 3–13. Complex Delay Block Parameters
Table 3–14. Complex Delay Block I/O Formats (Part 1 of 2)
© June 2010 Altera Corporation
Number of Pipeline Stages
Clock Phase Selection
Use Enable Port
Use Synchronous Clear Port
I
I/O
I1
I2
I3
Real([L1].[R1])Imag([L1].[R1])
[1]
[1]
Simulink (2),
Name
The Complex Delay block delays the incoming data by an amount specified by the
Number of Pipeline Stages parameter. The input must be a complex number.
Table 3–12
Table 3–12. Complex Delay Block Inputs and Outputs
Table 3–13
Table 3–14
(3)
d
ena
sclr
q
Signal
>= 1
User
Defined
On or Off
On or Off
I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
Value
shows the Complex Delay block inputs and outputs.
shows the Complex Delay block parameters.
shows the Complex Delay block I/O formats.
Input
Input
Input
Output
Specify the delay length of the block.
When you enable pipeline, you can indicate the phase selection with a binary
string, where a 1 indicates the phase in which the block is enabled. For
example:
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (sclr).
Direction
1—The block is always enabled and captures all data passing through the
block (sampled at the rate 1).
10—The block is enabled every other phase and every other data
(sampled at the rate 1) passes through.
0100—The block is enabled on the second phase of and only the second
data of (sampled at the rate 1) passes through. That is, the data on phases
1, 3, and 4 do not pass through the block.
Preliminary
Input data.
Optional clock enable.
Optional synchronous clear.
Delayed output data.
(Note 1)
VHDL
Description
Description
DSP Builder Standard Blockset Libraries
Implicit
Implicit
Type
(4)
3–9