IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 71

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Design Rules and Procedures
Loading Additional ModelSim Commands
Loading Additional ModelSim Commands
Making Quartus II Assignments to Block Entity Names
© June 2010 Altera Corporation
When you import HDL as a black box, DSP Builder creates a subdirectory
DSPBuilder<model name>_import. Any Tcl script *_add_msim.tcl in this subdirectory
automatically sources when you launch ModelSim.
You should not modify the generated scripts, but you can create you own scripts such
as <user name>_add_msim.tcl, which contain additional ModelSim commands that
you want to load into ModelSim.
The VHDL entity names of the blocks in a DSP Builder design are dependent on the
block’s parameter values. Blocks of the same type and same parameterization share a
common VHDL entity.
The entity names have the following format:
For example, a Delay block entity name:
Changing the parameterization of the block causes the entity name to change. If you
want to make an assignment to a block in the Quartus II project, and for the
assignment to remain when the block parameters change, you can use regular
expressions in the assignments.
For example, you may want to make a Preserve Registers assignment to the Delay
blocks in
Figure 3–25. Entity Name Assignment Example
Using the Quartus II Assignment Editor and Node Finder tools, you can identify the
names of the registers and make the assignments to them. For example, if your model
is my_model, the names may be:
<block type name>_GN<8 alphanumeric characters>
alt_dspbuilder_delay_GNLVAGVO3B
my_model_GN:auto_inst|alt_dspbuilder_delay_GNLVAGVO3B:Delay|alt_dsp
builder_SDelay:Delay1i|DelayLine
my_model_GN:auto_inst|alt_dspbuilder_delay_GNLVAGVO3B:Delay1|alt_ds
pbuilder_SDelay:Delay1i|DelayLine
Figure 3–25
to prevent them from merging.
Preliminary
DSP Builder Standard Blockset User Guide
3–27