IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 240

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–32
Table 2–48. Product Block Parameters
Table 2–49. Product Block I/O Formats (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Number of Pipeline
Stages
Clock Phase
Selection
Use Enable Port
Use Asynchronous
Clear Port
Use LPM
Use Dedicated
Circuitry
I/O
I
I1
I2
I3
I4
Name
[L1].[R1]
[L2].[R2]
[1]
[1]
Simulink (2),
Inferred,
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
>= 0
(Parameterizable)
User Defined
On or Off
On or Off
On or Off
On or Off
(3)
Table 2–49
Value
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L2 + R2 - 1} DOWNTO 0)
I3: in STD_LOGIC
I4: in STD_LOGIC
shows the Product block I/O formats.
Turn on to use the clock enable input (ena).
The bus number format that you want to use. Inferred means that the format is
automatically set by the format of the connected signal.
Specify the number of bits to the left of the binary point.
Specify the number of bits to the right of the binary point. This option applies only
to signed fractional formats.
The Pipeline represents the delay. The clock enable and asynchronous clear ports
are available only if the block is registered (that is, if the number of pipeline
stages is greater than or equal to 1).
This option is available only when the Pipeline value is greater than 0.
Specifies the phase selection with a binary string, where a 1 indicates the phase in
which the block is enabled. For example:
Turn on to use the asynchronous clear input (aclr).
When on, the Product block is mapped to the LPM_MULT library of
parameterized modules (LPM) function and the VHDL synthesis tool uses the
Altera LPM_MULT implementation.
When off, the VHDL synthesis tool uses the native * operator to synthesize the
product. If your design does not need arithmetic boundary optimization—such as
connecting a multiplier to constant combinational logic or register balancing
optimization—the LPM_MULT implementation generally yields a better result for
both speed and area.
Turn on to use the dedicated multiplier circuitry (if supported by your target
device). This option is ignored if not supported by your target device.
1—The block is always enabled and captures all data passing through the
block (sampled at the rate 1).
10—The block is enabled every other phase and every other data (sampled at
the rate 1) passes through.
0100—The block is enabled on the second phase of and only the second data
of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and
4 do not pass through the block.
(Note 1)
Preliminary
VHDL
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Explicit
Explicit
Type
Product
(4)