IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 365

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
True Dual-Port RAM
Table 9–37. True Dual-Port RAM Block Parameters (Part 1 of 2)
© June 2010 Altera Corporation
Number of words
Data Type
[number of bits].[]
[].[number of bits]
Name
c
The input address bus must be Unsigned. The clock enable signal (ena) bypasses
any output register.
If you write to the same address simultaneously with the a and b inputs, the data
written to the RAM is indeterminate (corrupt). In ModelSim simulations, the data at
this address is set to Unknown (all bits X). In DSP Builder simulation, the data at this
address is set to zero, and a warning is given:
If this data is read, DSP Builder warns that you are reading corrupt data:
If you execute a testbench comparison to hardware, you may get simulation
mismatches if you are making use of corrupt data in your design or outputting the
read memory contents to a pin.
Table 9–36
Table 9–36. True Dual-Port RAM Block Inputs and Outputs
Table 9–37
data_a
addr_a
wren_a
data_b
addr_b
wren_b
ena
q_a
q_b
>= 1
(Parameterizable)
Inferred,
Signed Integer,
Unsigned Integer,
Signed Fractional
>= 0
(Parameterizable)
>= 0
(Parameterizable)
"Warning: True Dual-Port RAM: simultaneous a and b side writing to
address <addr>. Memory contents at this address will be Unknown (X)
in hardware."
"Warning: True Dual-Port RAM: <a|b>-side reading corrupt RAM data at
address <addr>. Memory contents at this address will be Unknown (X)
in hardware."
Signal
Value
shows the True Dual-Port RAM block inputs and outputs.
shows the True Dual-Port RAM block parameters.
Input
Input
Input
Input
Input
Input
Input
Output
Output
Direction
Specify the address width in words.
The input data type format.
Specify the number of bits stored on the left side of the binary point.
Specify the number of bits to the right of the binary point. This option
applies only to signed fractional formats.
Preliminary
Input data port a
Address bus a.
Write enable a
Input data port b
Address bus b
Write enable b
Optional clock enable port
Output data port a
Output data port b
Description
Description
DSP Builder Standard Blockset Libraries
9–25