IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 183

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter :
Troubleshooting Issues
A Specified Path Cannot be Found or a File Name is Too Long
Incorrect Interpretation of Number Format in Output from MegaCore Functions
Simulation Mismatch For FIR Compiler MegaCore Function
Simulation Mismatch After Changing Signals or Parameters
Unexpected Exception Error when Generating Blocks
© June 2010 Altera Corporation
f
The maximum length for a path is limited to 256 characters in the Windows operating
system.
When the file path to a model or the name of the model is very long, DSP Builder may
attempt to create a file path exceeding this limit.
If this problem occurs, reduce the length of the file path to the model or the length of
its name.
For some MegaCore functions, DSP Builder may be unable to infer whether it should
interpret output signals as signed, unsigned, signed fractional. This issue can cause
problems when visualizing the output. For example, by directly attaching scopes,
when the signal waveform may obscur because of the incorrectly inferred number
formats.
Correct this issue by connecting to the output with an AltBus block or a
Non-synthesizable Output block (as appropriate) with the correct bus type
assignment.
FIR Compiler MegaCore function-generated functional simulation models generally
do not output valid data until the data storage of these models is clear.
For more information including a formula that estimates the number of cycles before
relevant samples are available, refer to the Simulate the Design section in the
Compiler User
The simulation results may not match after changing any signal names or parameters.
If this problem occurs, delete the previous testbench directory (tb_<model name>)
and run the simulation again.
DSP Builder issues errors of the following form when you generate a DSP Builder
system:
Info: IP Generator Info: stderr: No clock info for
Info: IP Generator Info: stderr: Failed to find clock
Info: IP Generator Info: stderr: Failed to find clock
Error: IP Generator Error: Unexpected exception thrown by MDLFactory:
Error: Node instance "dut" instantiates undefined entity
Guide.
"TestBarrelShifter" File: <path>/mytoplevel.vhd Line: 30
Preliminary
java.lang.NullPointerException
DSP Builder Standard Blockset User Guide
my_alt_dspbuilder_clock
my_alt_dspbuilder_clock
my_alt_dspbuilder_clock
FIR
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