IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 203

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 1: AltLab Library
Signal Compiler
Signal Compiler
Table 1–16. Signal Compiler Block Parameters Settings Page
© June 2010 Altera Corporation
Family
Use Board Block
to Specify Device
Compile
Scan JTAG
Program
Analyze
Synthesis
Fitter
Enable SignalTap II On or Off
SignalTap II depth
SignalTap II clock
Use Base Clock
Export
Name
f
1
1
Stratix
Stratix II, Stratix II GX,
Stratix III, Stratix IV,
Arria
Cyclone
Cyclone III
On or Off
List of ports connected to
the JTAG cable.
2, 4, 8, 16, 32, 64, 128,
256, 512, 1k, 2K, 4K, 8K
User defined
On or Off
You can double-click on the Resource Usage block to display more information
about the blocks in your design that generate hardware.
The information that displays depends on the selected device family. Refer to the
device documentation for more information.
Select the Timing tab and click Highlight path to highlight the critical paths on your
design.
When the source and destination in the dialog box are the same and you highlight a
single block, the critical path is because of the internal function or a feedback loop.
Use the Signal Compiler block to create and compile a Quartus II project for your
DSP Builder design, and to program your design onto an Altera
You must save your model file before you can use the Signal Compiler block.
Table 1–16
®
®
GX, Arria II GX,
, Stratix GX,
®
, Cyclone II,
Value
—
—
—
—
—
—
shows the controls and parameters for the Signal Compiler block.
The Altera device family you want to target.
If you use the automated design flow, the Quartus II software
automatically uses the smallest device in which your design fits.
Turn on to get the device information from the development board block.
Click to compile your design.
The required JTAG cable port.
Click to download your design to the connected development board.
Click to analyze the DSP Builder system.
Click to run Quartus II synthesis.
Click to run the Quartus II Fitter tool.
Turn on to enable use of a
in your design. Turn on this setting to add extra logic and memory to
capture signals in hardware in real time.
The required depth for the SignalTap II Logic Analyzer.
Specifies the clock to use for capturing data with the SignalTap II feature
from a list of available signals.
Turn on if you want to use the base clock for the SignalTap II Logic
Analyzer.
Exports synthesizable HDL to a user-specified directory.
Preliminary
SignalTap II Logic Analyzer
Description
DSP Builder Standard Blockset Libraries
®
FPGA.
block
1–13