IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 278

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–16
Table 4–24. LFSR Sequence Block Parameters (Part 2 of 2)
Table 4–25. LFSR Sequence Block I/O Formats
Figure 4–10. LFSR Sequence Block Example
Logical Bit Operator
Table 4–26. Logical Bit Operator Block Parameters
DSP Builder Standard Blockset Libraries
Use Enable Port
Use Synchronous
Clear Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
Logical Operator
Number of Inputs
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
[L].[R]
Name
Name
I1
I2
O1
O2
Table
[1].[0]
[1].[0]
[1].[0]
[L].[0]
is an input port. O1
Simulink (2),
4–25:
AND, OR, XOR,
NAND, NOR, NOT
1–16
(Parameterizable)
On or Off
On or Off
Table 4–25
Figure 4–10
The Logical Bit Operator block performs logical operations on single-bit inputs.
You can specify a variable number of inputs. If the integer is positive, it is interpreted
as a boolean 1, otherwise it is interpreted as 0. The number of inputs is variable.
Table 4–26
(3)
[L].[R]
Value
is an output port.
Value
shows the LFSR Sequence block I/O formats.
shows the Logical Bit Operator block parameters.
I1: in STD_LOGIC
I2: in STD_LOGIC
O1: out STD_LOGIC
O2: out STD_LOGIC_VECTOR(L-1 DOWNTO 0)
shows an example with the LFSR Sequence block.
Specify the operator you want to use.
Specify the number of inputs. This parameter defaults to 1 if the NOT logical
operator is selected.
(Note 1)
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (sclr).
Preliminary
VHDL
Description
Description
Chapter 4: Gate & Control Library
© June 2010 Altera Corporation
Logical Bit Operator
Type
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