IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 56

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–12
Figure 3–11. Magnitude Block: Combinational Behavior
Figure 3–12. Delay Block: Registered Behavior
DSP Builder Standard Blockset User Guide
Figure 3–11
The Magnitude block translates as a combinational signal in VHDL. DSP Builder
does not add clock pins to this function.
Figure 3–12
DSP Builder adds clock pin inputs to this function. The Delay block, with the Clock
Phase Selection parameter equal to 100, is converted into a VHDL shift register with a
decimation of three and an initial value of zero.
For feedback circuitry (the output of a block fed back into the input of a block), a
registered block must be in the feedback loop. Otherwise, DSP Builder creates an
unresolved combinational loop
illustrates DSP Builder block combinational behavior.
illustrates the behavior of a registered DSP block. In the VHDL netlist,
Preliminary
(Figure
3–13).
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
Frequency Design Rules