IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 362

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–22
Table 9–34. Single-Port RAM Block Parameters (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Number of words
Data Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Memory Block
Type
Initialization
Name
f
>= 1
(Parameterizable)
Inferred,
Signed Integer,
Unsigned Integer,
Signed Fractional
(Parameterizable)
(Parameterizable)
AUTO, M512, M4K,
M-RAM, M9K,
MLAB, M144K
Blank, From HEX file,
From MATLAB array
Use the Quartus II software to generate a .hex file that must be in your DSP Builder
working directory.
The data in a standard .hex file is formatted in multiples of eight and the output bit
width should also be in multiples of eight. The Quartus II software does allow you to
create non-standard .hex files but pads 1's to the front for negative numbers to make
them multiples of eight. Thus, large numbers with less bits may be treated as negative
numbers. A warning issues if you specify a non-standard .hex file. If you require a
different bit width, you should set the output bit width to the same as that in the .hex
file but use an
supports 32-bit addressing with extended linear address records in the .hex file.
For instructions on creating this file, refer to Creating a Memory Initialization File or
Hexadecimal (Intel-Format) File in the Quartus II Help.
The MATLAB array parameter must be a one dimensional MATLAB array with a
length less than or equal to the number of words. Specify the array from the MATLAB
work-space or directly in the MATLAB Array box.
Table 9–33
Table 9–33. Single-Port RAM Block Inputs and Outputs
Table 9–34
d
addr
wren
ena
q_a
Value
Signal
shows the Single-Port RAM block inputs and outputs.
shows the Single-Port RAM block parameters.
AltBus
Input
Input
Input
Input
Output
Specify the address width in words.
The input data type format.
Specify the number of bits stored on the left side of the binary point.
Specify the number of bits to the right of the binary point. This option applies
only to signed fractional formats.
The FPGA RAM memory block type. Some memory types are not available for
all device types. If you specify M-RAM, the RAM is always initialized to
unknown in the hardware and simultaneous read/writes to the same address
also give unknown in hardware. The unknowns are not modeled in
Simulink, and comparisons with ModelSim shows differences.
Specify the initialization. If Blank is selected, the contents of the RAM are
pre-initialized to zero.
Direction
block to convert to the required bit width. DSP Builder
Preliminary
Input data port.
Address bus.
Write enable.
Optional clock enable port
Output data port.
Description
Description
© June 2010 Altera Corporation
Chapter 9: Storage Library
Single-Port RAM