IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 276

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–14
Figure 4–7. If Statement Block Example
LFSR Sequence
Figure 4–8. Default LFSR Sequence Block with Length 8 Circuitry
DSP Builder Standard Blockset Libraries
Figure 4–7
conditional statement:
The LFSR Sequence block implements a linear feedback shift register that shifts one
bit across L registers. The register output bits shift from LSB to most significant bit
(MSB) with the output sout connected to the MSB of the shift register. The register
output bits can optionally be XORed or XNORed together.
For example, when choosing an LFSR sequence of length eight, the default
polynomial is x8 + x4 + x3 + x2 + 1 with the circuitry that
In this default structure:
■
■
■
■
You can modify the implemented LFSR sequence by changing the parameter values.
Quantizer:
if (Input<-4)
else if ((Input>=-4) & (Input<10)) Output = 0
else Output = 100
The polynomial is a primitive or maximal-length polynomial
All registers are initialized to one
The feedback gate type is XOR
The feedback structure is an external n-input gate or many to one
shows an example of the If Statement block, which implements the
Output = -100
Preliminary
Figure 4–8
Chapter 4: Gate & Control Library
© June 2010 Altera Corporation
shows.
LFSR Sequence