IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet - Page 60

• Manufacturer Part Number: IPTR-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPTR-DSPBUILDER

• Function: DSP Builder
• License: Renewal License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–16
Timing Semantics Between Simulink and HDL Simulation
Simulink Simulation Model
HDL Simulation Models
DSP Builder Standard Blockset User Guide
1
1
DSP Builder uses Simulink to simulate the behavior of hardware components.
However, there are some fundamental differences between the step-based simulation
in Simulink and the event-driven simulation that VHDL and Verilog HDL designs
use.
This section describes the timing semantics that DSP Builder uses for translating
between the Simulink and HDL environments.
To ensure correlation between the HDL and Simulink simulation, you must use a
discrete fixed or variable-step solver in Simulink.
Use a fixed-step solver for a single clock domain design or a variable-step solver for
multiple-clock domain designs.
Configure the solver timing mode in the Configuration Parameters dialog box from
the Simulation menu in Simulink. Each step is a discrete unit of simulation. DSP
Builder quantizes the clock in an idealized manner as a cycle counter.
At the beginning of each step, Simulink provides each block with inputs that you
know. DSP Builder evaluates functions and propagates the resultant outputs in the
current step. The outputs of your model are the results of all these computations.
For all steps, Simulink blocks produce output signals. Outputs varying based on
inputs received in the same step are referred to as direct feedthrough. Some DSP
Builder blocks may include direct feedthrough outputs, depending on the
parameterization of each block.
DSP Builder drives hardware simulation with a clock signal and the available input
stimuli. The TestBench block’ s testbench script feeds input signals to the HDL
simulator that maintain correlation between the HDL and Simulink simulation.
Simulation models in the DSP Builder libraries evaluate their logic on positive clock
edges. To avoid any timing conflicts, external inputs transition on negative clock
edges. DSP Builder updates registered outputs on positive clock edges. The
TestBench block-generated inputs arrive on negative clock edges, causing an
apparent half-cycle delay in the arrival of output
The HDL simulation in ModelSim should run over the same time as the Simulink
simulation. Generally DSP Builder aligns the timing so that ModelSim simulation
finishes at the end of the stimulus data. However, occasionally when using multiple
clocks, the rounding calculation that aligns the clock signals may set ModelSim
simulation to run for one additional clock cycle (on the fastest clock). You may receive
an unexpected end of file error message because there is no stimulus data for
this extra cycle.
Preliminary
Timing Semantics Between Simulink and HDL Simulation
(Figure 3–17 on page
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
3–18).